Electronics

DDR5 Memory Standards, Simulation And Design

Guests Randy White, Stephen Slater | Uploaded : 12/12/2023


The EEcosystem Podcast

DDR5 Memory Standards, Simulation And Design

In this episode, Randy White and Stephen Slater of Keysight Technologies join me to take a deep dive into DDR5 Memory and how to best design and simulate memory. We also talk about understanding and tapping into the full ecosystem that supports this technology that can help equip you to embrace memory design. (More on this subject will be covered in a Webinar hosted on September 13th. See link below).

 

Links & Resources

September 13th Live Webinar: PathWave ADS 2023 for High-Speed Digital Design and Simulation (keysight.com)

 

White Paper: The Road to DDR5

https://www.keysight.com/us/en/assets/7121-1105/white-papers/The-Road-to-DDR5.pdf

 

Application Note: Designing Leading-Edge Memory Systems

https://www.keysight.com/us/en/assets/3121-1298/application-notes/Designing-Leading-Edge-Memory-Systems.pdf

 

PCB Guidelines for Memory Interfaces (Xilinx)

PCB Guidelines for Memory Interfaces • UltraScale Architecture PCB Design User Guide (UG583) • Reader • Documentation Portal (xilinx.com)

Additional Resource Links:

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For SI/PI/EMI News and Technical Resources and to register for a free subscription visit the Signal Integrity Journal today.

 

For free Technical Resources and to Learn more about Keysight Pathwave EDA Software Solutions visit their homepage now.

 

For Custom RF and MW PCBs visit the Transline Technology Website to learn more.

Visit Summit Interconnect for all your PCB manufacturing needs.

 

Transcript